The present invention relates to a memory device which is suitable for use as a SRAM (Static Random Access Memory), etc., and more particularly to a memory device that uses as a memory cell a transistor, such as an RHET (Resonant-tunneling Hot Electron Transistor), an RBT (Resonance Bipolar Transistor), or others, having negative differential and threshold characteristics, a method for reading information from the memory device, and a method for writing information in the memory device.
Semiconductor memories have been increasingly large-scaled in recent years, and 64 Mb-DRAMs (Dynamic Random Access Memories) and 16 Mb-SRAMs have been developed. However, the presently used memory cell structures are a limit to higher densities of the semiconductor memories. Novel semiconductor memory cells which will enable higher densities for semiconductor memories are expected.
In general, each memory cell of a DRAM includes a capacitor utilizing the junction capacitance of a FET (Field Effect Transistor) for storage of information, and a FET which writes/reads information in/from the capacitor. A SRAM uses a flip-flop memory cell structure and usually includes six FETs.
Thus, a SRAM requires an area for at least 6 FETs. This is a limit to further miniaturization of the SRAM.